grelsec-design

Welcome to Grelsec Design Technologies

A leader in secure and reliable chip design tools and methodology development.

We provide services in full chip ASIC Design flow (RTL to GDS-II generation). Our objective is to provide services in physical design tool and methodology development in order to make secure and reliable chip (or GDS-II). We also provide services in Analog and Mixed Signal/RF IC (Custom IC Design) design solutions for several IP creation such as DDR memory interface, clocking (PLL/DLL), SerDes, High Speed I/O (HSIO), General Purpose I/O (GPIO), data converters (ADC/DAC), signal conditioning filters etc.

ASIC Design (RTL to GDSII)

Our services can be listed as follows:

1. Physical Design - Construction, Validation, Sign-off
   1. Floorplanning/PDN Design
   2. Placement
   3. Routing
   4. CTS
2. Physical Design - Timing/Area/Power sign-off
3. Physical Design - Security/Verification/Sign-off
   1. Side-Channel Analysis - PSC, EMSC, OSC
   2. Fault Injection - TFI, VFI, LFI, EMFI, Clock-glitch
4. Physical Design - Reliability/Verification/sign-off
   1. IR drop - interconnect
   2. Electromigration - interconnect
   3. ESD - Peripheral
   4. NBTI/PBTI - device layer
   5. HCI - device layer
5. Physical Design - Manufacturability/Verification/Sign-off
   1. DRC
   2. ERC
   3. LVS
   4. Antenna Rule Check
   5. Parasitic Extraction

Custom IC Design

Our services can be listed as follows:

1. Schematic Design
2. Custom Layout Design
3. Simulation with support for:
   1. High sigma simulation
   2. Monte-Carlo Simulation
   3. Enhanced fast simulation
4. Physical Verification
   1. DRC
   2. LVS
   3. ERC
   4. Antenna Rule Check
   5. Parasitic Extraction
5. Sign-off
   1. Aging
   2. Reliability - IR drop, Electromigration
   3. ESD
   4. Electromagnetic Induction (EMI)

For more details contact: grelsec.design@gmail.com